Academic Qualification

Ph.D. in University of Massachusetts, Amherst, MA

MBA in Sloan Fellows Program, MIT Sloan School of Management, MA

Master in University of Massachusetts, Amherst, MA

Bachelor in National Taiwan University, Taipei

Teaching Area

Electronics

Computational Algorithms

Data structure

IoTs

Machine learning

Solid State Electronics

Semiconductor Physics

Research Area

Advanced CMOS technology

AIoT solutions with AI

IoT and spatial intelligence technologies

Micro- and nano-electronics

Professional Services

•             Board of Governor, IEEE Electron Devices Society (2023-present)

•             Chair, IEEE Electron Devices Society, Award fundraising committee (2023-present)

•             Chair, IEEE Electron Devices Society, Special project committee (2022-present)

•             Member of Advisory Committee of the Hong Kong Trade and Development Council Electronics/Electrical Appliances Industries (2022-present).

•             Member of Industrial Advisory Committee, Applied Physics and Dept. Of EEE, Hong Kong Polytechnic University (2022-present)

•             Member of External Advisory Committee, Macau University of Science and Technology, Faculty of Information Technology (2019-present)

•             Member of Industrial Advisory Committee, Research Institute for Intelligent Wearable System RI-IWEAR), The Hong Kong Polytechnic University (2022-present)

•             Technical Advisor for Hong Kong Smart City Consortium (2017-present)

•             Chair of the IEEE Electronic Devices Society (EDS) Education award committee (2013-2017)

•             Chair of the IEEE Ernst Weber Managerial Leadership Award committee (2013)

•             Member of the IEEE EDS Electronic Material Committee and IEEE EDS membership committee (2013-2017)

•             Editor, IEEE Transactions on Electron Devices (2010-2016).

•             Member of Advisory Committee, Macao SAR Science and Technology Development Fund (5/20117-11/2019)

•             Hong Kong UGC Research Assessment Exercise 2020 – Member of the Electrical & Electronic Engineering Panel (2018-2022)

•             Member of the HKU Space Advisory Committee on Innovation and Technology (2019-2021)

•             Executive Committee Members (2018-2019) Communication Association of Hong Kong (CAHK) Steering Committee Member of the 2018 Hong Kong ICT Awards.

•             Assessment Panel Member of the Hong Kong ITC Enterprise Support Scheme (ESS) (2017-2023)

•             Board of Director of Co-operatives of Innovative Intellectual, Hong Kong. (2017-2021)

•             Board of Governor of the IEEE Electronic Devices Society (EDS) (2016-2018)

•             Guest editor for the special issue on “Advanced Silicon Technology”, IBM Journal of Research and Development, Vol. 50, No. 4/5, June 2006.

•             Served in the Technology Advisory Broad (TAB) on CMOS and Technology in Semiconductor Research Corporation (SRC)

•             “Research Needs for Novel Devices,” May 2003 Edition, 2002 Novel Device Task Force, Nanostructure & Integration Sciences, Semiconductor Research Corporation

•             Members of 2005 International Technology Roadmap for Semiconductor, Front-end Process Working Sub-Group

•             General Chair of the IEEE International Electron Devices Meeting (IEDM) (2010)

•             Technical Program committee members in several international conferences including IEDM (2002-2010), VLSI Technology Symposium (2005-2007), VLSI-TSA Symposium (Taiwan) (2006-2014), International Workshop on Computational Electronics (2009), International Conference on Solid-State and Integrated-Circuit Technology, China (2004)

Working Experience

Sep. 2025 ~ present, Distinguished Professor, School of Computer Science and Engineering, Faculty of Innovation Engineering, MUST

2022 ~ Present, Chairman, Simbury Limited & Simbury InnoTek Limited

2021 to 8/2025, Founding Chairman, Semiconductor Nanotechnology Alliance (Non-Profit)

2021 to Present, Board Director, Giant Technologies Company Limited

2019 to 2022, CEO, United Microelectronics Centre (Hong Kong) Limited

2016 to 2019, CTO, Hong Kong Applied Science and Technology Research Institute (ASTRI)

2013 to 2015, Vice President, Taiwan Semiconductor Manufacturing Company (TSMC), Europe BV

2013 to 2013, Visiting Research Scientist at MIT Microsystems Technology Laboratories

2007 to 2015, Director, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu

1996 to 2007, Senior Manager, IBM, NY

Academic Publication

1.             Oldiges, Phil and Dennard, Robert and Heidel, Dave and Klaasen, Bill and Assaderaghi, Fariborz and Ieong, Meikei, Theoretical determination of the temporal and spatial structure of/spl alpha/-particle induced electron-hole pair generation in silicon, IEEE Transactions on Nuclear Science, 47, (6), :2575--2579, 2000, IEEE.

2.             Nowak, EJ and Rainey, BA and Fried, DM and Kedzierski, J and Ieong, M and Leipold, W and Wright, J and Breitwisch, M, A functional FinFET-DGCMOS sram cell, Digest. International Electron Devices Meeting,, :411--414, 2002.

3.             Rim, K and Chan, K and Shi, L and Boyd, D and Ott, J and Klymko, N and Cardone, F and Tai, L and Koester, S and Cobb, M and others, Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs, IEEE International Electron Devices Meeting 2003, :3--1, 2003.

4.             Kedzierski, Jakub and Boyd, Diane and Zhang, Ying and Steen, Michelle and Jamin, Fen F and Benedict, John and Ieong, Meikei and Haensch, Wilfried, Issues in NiSi-gated FDSOI device integration, IEEE International Electron Devices Meeting 2003, :18--4, 2003.

5.             Chang, Mi-Chang and Chang, Chih-Sheng and Chao, Chih-Ping and Goto, Ken-Ichi and Ieong, Meikei and Lu, Lee-Chung and Diaz, Carlos H, Transistor-and circuit-design optimization for low-power CMOS, IEEE Transactions on Electron Devices, 55, (1), :84--95, 2007, IEEE.

6.             Chen, KN and Hoivik, N and Lin, CY and Young, A and Ieong, M and Shahidi, G, Investigations of Wafer Scale Etching with Xenon Difluoride, APS March Meeting Abstracts, :Q1--268, 2006.

7.             Ieong, Meikei and Jones, Erin C and Kanarsky, Thomas and Ren, Zhibin and Dokumaci, Omer and Roy, Ronnen A and Shi, Leathen and Furukawa, Toshiharu and Taur, Yuan and Miller, Robert J and others, Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs, International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), :19--6, 2001.

8.             Ku, V and Amos, R and Steegen, A and Cabral, C Jr and Narayanan, V and Jamison, P and Nguyen, P and Li, Y and Gribelyuk, M and Wang, Y and others, Low Tinv (< 1.8 nm) metal-gated MOSFETs on SiO2 based gate dielectrics for high performance logic applications, Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, :730, 2003.

9.             Wang, Xinlin and Shang, Huiling and Oldiges, Phil and Rim, Ken and Koester, Steve and Ieong, Meikei, Hole Mobility Enhancement Modeling and Scaling Study for High Performance Strained Ge Buried Channel PMOSFETs, Simulation of Semiconductor Processes and Devices 2004, :65--68, 2004, Springer Vienna Vienna.

10.         Ellis-Monaghan, John and Lee, Kam-Leung and Ieong, Meikei and Yang, Isabel, Carbon implanted halo for super halo characteristic NFETs in bulk and SOI, European Solid-State Device Research Conference, 2001.

11.         Ieong, Meikei, Ultra-thin silicon channel single-and double-gate MOSFETs, Symposium of Solid-State Devices and Mateirals, 2002.

12.         Yang, M and Chan, V and Ku, SH and Ieong, M and Shi, L and Chan, KK and Murthy, CS and Mo, RT and Yang, HS and Lehner, EA and others, On the integration of CMOS with hybrid crystal orientations, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., :160--161, 2004.

13.         Ieong, Mei-Kei and Tang, Ting-Wei, Distributed Algorithms for Three-dimensional Semiconductor Device Simulations, VLSI Design, 6, (1-4), :123--126, 1998, Hindawi Publishing Corporation.

14.         Luo, Z and Rovedo, N and Ong, S and Phoong, B and Eller, M and Utomo, H and Ryou, C and Wang, H and Stierstorfer, R and Clevenger, L and others, High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology, 2007 IEEE Symposium on VLSI Technology, :16--17, 2007.

15.         Yang, SH and Sheu, JY and Ieong, MK and Chiang, MH and Yamamoto, T and Liaw, JJ and Chang, SS and Lin, YM and Hsu, TL and Hwang, JR and others, 28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications, 2011 IEEE Custom Integrated Circuits Conference (CICC), :1--5, 2011.

16.         Oldiges, Phil and Lin, Qimghuamg and Petrillo, Karen and Sanchez, Martha and Ieong, Meikei and Hargrove, Mike, Modeling line edge roughness effects in sub 100 nanometer gate length devices, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No. 00TH8502), :131--134, 2000.

17.         Lee, K and Frank, M and Paruchuri, V and Cartier, E and Linder, B and Bojarczuk, N and Wang, X and Rubino, J and Steen, M and Kozlowski, P and others, Poly-Si/AlN/HfSiO stack for ideal threshold voltage and mobility in sub-100 nm MOSFETs, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :160--161, 2006.

18.         Ieong, M and Sudijono, J and Ku, JH and Shum, D and Hierlemann, M and Amos, R and Chiulli, G and Lindsay, R and Kim, SD and Loesing, R and others, Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices, 2006 International Electron Devices Meeting, :1--4, 2006.

19.         Ieong, Meikei, A multi-valley hydrodynamic transport model for GaAs extracted from self-consistent Monte Carlo data, 1993.

20.         Rim, K and Anderson, R and Boyd, D and Cardone, F and Chan, K and Chen, H and Christansen, S and Chu, J and Jenkins, K and Kanarsky, T and others, Strained Si CMOS (SS CMOS) technology: opportunities and challenges, Solid-State Electronics, 47, (7), :1133--1139, 2003, Pergamon.

21.         Yin, Haizhou and Ren, Z and Chen, H and Holt, J and Liu, X and Sleight, J and Rim, K and Chan, V and Fried, D and Kim, Y and others, Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :76--77, 2006.

22.         Skotnicki, T and Kasai, N and Dosho, S and Clinton, M and Zhang, K and Calhoun, B and Ieong, M and Rim, K and Kosonocky, S and Matsuzawa, A and others, Rump Sessions Tuesday, June 14,.

23.         Doris, B and Ieong, M and Zhu, T and Zhang, Y and Steen, M and Natzle, W and Callegari, S and Narayanan, V and Cai, J and Ku, SH and others, Device design considerations for ultra-thin SOI MOSFETs, IEEE International Electron Devices Meeting 2003, :27--3, 2003.

24.         Ouyang, Christine and Madan, Anita and Klymko, Nancy and Li, Jinghong and Murphy, Richard and Wildman, Horatio and Davis, Robert and Murray, Conal and Holt, Judson and Panda, Siddhartha and others, Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain, MRS Online Proceedings Library, 913, (1), :102, 2005, Springer International Publishing Cham.

25.         Young, R and Su, L and Ieong, M and Kapur, S, A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET, IEEE Electron Device Letters, 19, (7), :234--236, 1998, IEEE.

26.         Ieong, Meikei, Welcome from the general chair, 2010 International Electron Devices Meeting, :1--1, 2010.

27.         Kedzierski, Jakub and Ieong, Meikei and Nowak, Edward and Kanarsky, Thomas S and Zhang, Ying and Roy, Ronnen and Boyd, Diane and Fried, David and Wong, H-SP, Extension and source/drain design for high-performance FinFET devices, IEEE Transactions on Electron Devices, 50, (4), :952--958, 2003, IEEE.

28.         Kedzierski, Jakub and Ieong, Meikei and Kanarsky, Thomas and Zhang, Ying and Wong, H-SP, Fabrication of metal gated FinFETs through complete gate silicidation with Ni, IEEE transactions on electron devices, 51, (12), :2115--2120, 2004, IEEE.

29.         Ren, Zhibin and Sleight, J and Hergenrother, JM and Singh, DV and Gluschenkov, O and Dokumaci, O and Black, L and Pan, J and Lee, K-l and Ott, J and others, Ultra-Thin SOI CMOS Using Laser Spike Anneal, 2006 International Symposium on VLSI Technology, Systems, and Applications, :1--2, 2006.

30.         Ieong, MeiKei and Young, Ralph and Park, Heemyong and Yang, Werner RanusIsabel and Fung, Samuel and Assaderaghi, Fariborz and AssaderaghiWong, Fariborz and Wong, HS Philip, Modeling the impact of body-to-body leakage in partially-depleted SOI CMOS technology, Simulation of Semiconductor Processes and Devices 2001: SISPAD 01, :230--233, 2001, Springer Vienna Vienna.

31.         Gusev, EP and Cabral, C and Under, BP and Kim, YH and Maitra, K and Carrier, E and Nayfeh, H and Amos, R and Biery, G and Bojarczuk, N and others, Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/dielectrics: Enhanced performance at reduced gate leakage, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., :79--82, 2004.

32.         Ieong, Mei-Kei and Tang, Tw, A general hydrodynamic solver for deep submicron silicon devices, Proc. Int. Workshop on Computational Electronics, :111--114, 1994.

33.         Fried, DM and Hergenrother, JM and Topol, AW and Chang, L and Sekaric, L and Sleight, JW and McNab, SJ and Newbury, J and Steen, SE and Gibson, G and others, Aggressively scaled (0.143/spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., :261--264, 2004.

34.         Narayanan, V and Callegari, A and McFeely, FR and Nakamura, K and Jamison, P and Zafar, S and Cartier, E and Steegen, A and Ku, V and Nguyen, P and others, Dual work function metal gate CMOS using CVD metal electrodes, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., :192--193, 2004.

35.         Ieong, Meikei and Doris, Bruce and Kedzierski, Jakub and Rim, Ken and Yang, Min, Silicon device scaling to the sub-10-nm regime, Science, 306, (5704), :2057--2060, 2004, American Association for the Advancement of Science.

36.         Chen, Kuan-Neng and Lee, Sang Hwui and Andry, Paul S and Tsang, Cornelia K and Topol, Anna W and Lin, Yu-Ming and Lu, Jian-Qiang and Young, Albert M and Ieong, Meikei and Haensch, Wilfried, Structure, design and process control for Cu bonded interconnects in 3D integrated circuits, 2006 International Electron Devices Meeting, :1--4, 2006.

37.         Singh, DV and Jenkins, Keith A and Sleight, J and Ren, Z and Ieong, M and Haensch, W, Strained ultrahigh performance fully depleted nMOSFETs with f/sub t/of 330 GHz and sub-30-nm gate lengths, IEEE electron device letters, 27, (3), :191--193, 2006, IEEE.

38.         Lee, KL and Cardone, F and Saunders, P and Kozlowski, P and Ronsheim, P and Zhu, H and Li, J and Chu, J and Chan, K and Ieong, M, 20 nm N/sup+/abrupt junction formation in strained Si/Si/sub 1-x/Ge/sub x/MOS device, IEEE International Electron Devices Meeting 2003, :20--1, 2003.

39.         Oldiges, P and Bernstein, K and Heidel, D and Klaasen, B and Cannon, E and Dennard, R and Tang, H and Ieong, M and Wong, H-SP, Soft error rate scaling for emerging SOI technology options, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No. 01CH37303), :46--47, 2002.

40.         Topol, Anna W and La Tulipe, DC and Shi, L and Alam, SM and Frank, DJ and Steen, SE and Vichiconti, J and Posillico, D and Cobb, M and Medd, S and others, Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs), IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., :352--355, 2005.

41.         Ieong, Meikei, Nano-CMOS scaling: Novel devices and materials, 2006 IEEE Nanotechnology Materials and Devices Conference, 1, :88--89, 2006.

42.         Kedzierski, Jakub and Boyd, Diane and Cabral, C and Ronsheim, Paul and Zafar, Sufi and Kozlowski, Paul M and Ott, John A and Ieong, Meikei, Threshold voltage control in NiSi-gated MOSFETs through SIIS, IEEE transactions on electron devices, 52, (1), :39--46, 2005, IEEE.

43.         Shang, Huiling and Rubino, J and Doris, B and Topol, A and Sleight, J and Cai, J and Chang, L and Ott, A and Kedzierski, J and Chan, K and others, Mobility and CMOS devices/circuits on sub-10nm [110] ultra thin body SOI, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., :78--79, 2005.

44.         Ieong, Meikei and Oldiges, Phil, Technology modeling for emerging SOI devices, IEICE Transactions on Electronics, 86, (3), :301--307, 2003, The Institute of Electronics, Information and Communication Engineers.

45.         Shang, Huiling and Chu, Jack O and Bedell, Stephen and Gusev, Evgeni P and Jamison, Paul and Zhang, Ying and Ott, John A and Copel, Matthew and Sadana, Devendra and Guarini, Kathryn W and others, Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., :157--160, 2004.

46.         Tang, Ting-Wei and Gan, Haitao and Ieong, MeiKei, Re-examination of the hot-carrier transport model using spherical harmonic expansion of the Boltzmann transport equation, 1998 Sixth International Workshop on Computational Electronics. Extended Abstracts (Cat. No. 98EX116), :238--241, 1998.

47.         Yang, Min and Gusev, Evgeni P and Ieong, Meikei and Gluschenkov, Oleg and Boyd, Diane C and Chan, Kevin K and Kozlowski, Paul M and D'Emic, Christopher P and Sicina, Raymond M and Jamison, Paul C and others, Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO 2 gate dielectrics, IEEE Electron Device Letters, 24, (5), :339--341, 2003, IEEE.

48.         Chang, Leland and Ieong, Meikei and Yang, Min, CMOS circuit performance enhancement by surface orientation optimization, IEEE Transactions on Electron Devices, 51, (10), :1621--1627, 2004, IEEE.

49.         Wang, Xinlin and Rim, Ken and Shang, Huiling and Koester, Steve and Oldiges, Phil and Ieong, Meikei, Strained SiGe/Ge Buried Channel pMOSFETs Design For High Performance Applications, 2006 64th Device Research Conference, :75--76, 2006.

50.         Ouyang, Qiqing and Ieong, Meikei and Fischetti, Massimo and Panda, Siddhartha and Boyd, Diane and Rim, Ken and Ott, John A, Characteristics of high performance PFETs with embedded SiGe source/drain and< 100> channels on 45/spl deg/rotated wafers, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005.(VLSI-TSA-Tech)., :27--28, 2005.

51.         Ieong, Meikei, General hydrodynamic equation solver and its application to submicrometer semiconductor device simulations, 1996.

52.         Ieong, Meikei and Tang, Ting-Wei, Influence of hydrodynamic models on the prediction of submicrometer device characteristics, IEEE Transactions on Electron Devices, 44, (12), :2242--2251, 1997, IEEE.

53.         Frank, David J and Taur, Yuan and Ieong, Meikei and Wong, H-SP, Monte Carlo modeling of threshold variation due to dopant fluctuations, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No. 99CH36326), :171--172, 1999.

54.         Pan, James and Topol, Anna and Shao, Ingrid and Singh, Dinkar and Ren, Zhibin and Sung, C-Y and Ieong, Meikei and Pellerin, John and Iacoponi, John and Lin, M-R, Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :184--185, 2006.

55.         Shang, H and Chu, JO and Wang, X and Mooney, PM and Lee, K and Ott, J and Rim, K and Chan, K and Guarini, K and Ieong, M, Channel design and mobility enhancement in strained germanium buried channel MOSFETs, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., :204--205, 2004.

56.         Ieong, Meikei and Dons, B and Kedzierski, Jakub and Ren, Zhibin and Rim, Ken and Yang, Min and Shang, Huiling, Scaling beyond conventional CMOS device, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004., 1, :31--34, 2004.

57.         Sheraw, CD and Yang, M and Fried, DM and Costrini, G and Kanarsky, T and Lee, W-H and Chan, V and Fischetti, MV and Holt, J and Black, L and others, Dual stress liner enhancement in hybrid orientation technology, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., :12--13, 2005.

58.         Ieong, Meikei, IEDM Executive Committee, 2010 International Electron Devices Meeting, :1--5, 2010.

59.         Yin, Haizhou and Ren, Z and Saenger, KL and Hovel, HJ and De Souza, JP and Ott, JA and Zhang, R and Bedell, SW and Pfeiffer, G and Bendernagel, R and others, Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, :136--138, 2006.

60.         Kedzierski, Jakub and Nowak, Edward and Ieong, Meikei and Kanarsky, Thomas and Boyd, Diane, Dual Workfunction Metal-Gate FinFET Devices Fabricated Using Total Gate Silicidation, SOLID STATE DEVICES AND MATERIALS, :6--7, 2003, Business Center for Academic Societies; 1998.

61.         Oldiges, Phil and Wang, Xinlin and Ieong, MeiKei and Fischer, Stephen and Rim, Ken, A practical approach to modeling strained silicon NMOS devices, Simulation of Semiconductor Processes and Devices 2001: SISPAD 01, :292--295, 2001, Springer Vienna Vienna.

62.         Rim, Kern and Chu, J and Chen, H and Jenkins, Keith A and Kanarsky, T and Lee, K and Mocuta, A and Zhu, H and Roy, R and Newbury, J and others, Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No. 01CH37303), :98--99, 2002.

63.         Tang, Ting-Wei and Wang, Xinlin and Gan, Haitao and Ieong, Meikei, An analytic expression of thermal diffusion coefficient for the hydrodynamic simulation of semiconductor devices, VLSI Design, 13, (1-4), :131--134, 2001, Hindawi Publishing Corporation.

64.         Ren, Zhibin and Solomon, Paul M and Kanarsky, Thomas and Doris, Bruce and Dokumaci, Omer and Oldiges, Phil and Roy, Ronnen A and Jones, Erin C and Ieong, Meikei and Miller, Robert J and others, Examination of hole mobility in ultra-thin body SOI MOSFETs, Digest. International Electron Devices Meeting,, :51--54, 2002.

65.         Kedzierski, J and Ieong, MeiKei and Xuan, Peiqi and Bokor, J and King, Tsu-Jae and Hu, Chenming, Design analysis of thin-body silicide source/drain devices, 2001 IEEE International SOI Conference. Proceedings (Cat. No. 01CH37207), :21--22, 2001.

66.         Rim, Kern and Koester, S and Hargrove, M and Chu, J and Mooney, PM and Ott, J and Kanarsky, T and Ronsheim, P and Ieong, M and Grill, A and others, Strained Si NMOSFETs for high performance CMOS technology, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No. 01 CH37184), :59--60, 2001.

67.         Nayfeh, HM and Singh, DV and Hergenrother, JM and Sleight, JW and Ren, Z and Dokumaci, O and Black, L and Chidambarrao, D and Venigalla, R and Pan, J and others, Silicon and Elemental Semiconductor Devices-Effect of Tensile Uniaxial Stress on the Electron Transport Properties of Deeply Scaled FD-SOI n-Type MOSFETs, IEEE Electron Device Letters, 27, (4), :288--290, 2006, New York: Institute of Electrical and Electronics Engineers, c1979 [ie c1980]-.

68.         Ieong, MeiKei and Logan, Ronald and Slinkman, James, Efficient quantum correction model for multi-dimensional CMOS simulations, Simulation of Semiconductor Processes and Devices 1998: SISPAD 98, :129--132, 1998, Springer Vienna Vienna.

69.         Ieong, MeiKei and Wong, H-SP and Taur, Yuan and Oldiges, Phil and Frank, David, DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No. 00TH8502), :147--150, 2000.

70.         Guarini, KW and Topol, AT and Ieong, M and Bernstein, K and Xiu, K and Joshi, RV and Yu, R and Shi, L and Newport, MR and Singh, DV and others, The impact of wafer-level layer transfer on high performance devices and circuits for 3D fabrication, Proceedings of Electrochemical Society (ECS) Annual Meeting, Paris, France, Abstract, 431, :2003--20, 2003.

71.         Shang, H and Chang, L and Wang, X and Rooks, M and Zhang, Y and To, B and Babich, K and Totir, G and Sun, Y and Kiewra, E and others, Investigation of FinFET devices for 32nm technologies and beyond, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :54--55, 2006.

72.         Wong, H-SP and Doris, B and Gusev, E and Ieong, M and Jones, EC and Kedzierski, J and Ren, Z and Rim, K and Shang, H, Recent progress in devices and materials for CMOS technology, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers.(IEEE Cat. No. 03TH8672), :13--16, 2003.

73.         Nayfeh, HM and Singh, DV and Hergenrother, JM and Sleight, JW and Ren, Z and Dokumaci, O and Black, L and Chidambarrao, D and Venigalla, R and Pan, J and others, Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs, IEEE electron device letters, 27, (4), :288--290, 2006, IEEE.

74.         Fang, S and Tan, SS and Dyer, T and Luo, Z and Yan, J and Kim, JJ and Rovedo, N and Lun, Z and Yuan, J and Chen, X and others, Process induced stress for CMOS performance improvement, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, :108--111, 2006.

75.         Jones, Erin C and Ieong, Meikei and Kanarsky, Thomas and Dokumaci, Omer and Roy, Ronnen A and Shi, Leathen and Furukawa, Toshiharu and Miller, Robert J and Wong, HS Philip, High performance of planar double gate MOSFETs with thin backgate dielectrics, Device Research Conference. Conference Digest (Cat. No. 01TH8561), :28--29, 2001.

76.         Oldiges, P and Dennard, R and Heidel, D and Klaasen, B and Assaderaghi, F and Ieong, M, SELECTED PAPERS FROM THE 2000 IEEE NUCLEAR AND SPACE RADIATION EFFECTS CONFERENCE (NSREC'00)-Reno, Nevada, July 24-28, 2000-Session J: SINGLE EVENT EFFECTS, MECHANISMS AND MODELING-Theoretical, IEEE Transactions on Nuclear Science, 47, (6), :2575--2579, 2000, New York, NY: Professional Technical Group on Nuclear Science, c1963-.

77.         KEDZIERSKI, Jakub and IEONG, Meikei and NOWAK, Edward, Issues in high performance FinFET and FDSOI transistor design, Proceedings-Electrochemical Society, :185--196, 2003.

78.         Ieong, Meikei and Narayanan, Vijay and Singh, Dinkar and Topol, Anna and Chan, Victor and Ren, Zhibin, Transistor scaling with novel materials, Materials today, 9, (6), :26--31, 2006, Elsevier.

79.         Kedzierski, Jakub and Boyd, Diane and Ronsheim, Paul and Zafar, Sufi and Newbury, J and Ott, John and Cabral, C and Ieong, M and Haensch, Wilfried, Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS), IEEE International Electron Devices Meeting 2003, :13--3, 2003.

80.         Chan, KK and Yang, M and Shi, L and Kumar, A and Ott, JA and Patel, J and Schultz, R and Kry, H and Zhang, Y and Sikorski, E and others, Silicon on Insulator CMOS with Hybrid Crystal Orientation Using Double Wafer Bonding, 2006 64th Device Research Conference, :41--42, 2006.

81.         Kedzierski, Jakub and Fried, David M and Nowak, Edward J and Kanarsky, Thomas and Rankin, Jed H and Hanafi, Hussein and Natzle, Wesley and Boyd, Diane and Zhang, Ying and Roy, Ronnen A and others, High-performance symmetric-gate and CMOS-compatible V/sub t/asymmetric-gate FinFET devices, International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), :19--5, 2001.

82.         Ieong, Mei-Kei and Tang, Ting-Wei, Influence of hydrodynamic models on the simulated characteristics of deep submicron SOI-MOSFETs, Proceedings. IEEE International SOI Conference, :51--52, 1994.

83.         Lee, BH and Mocuta, A and Bedell, S and Chen, H and Sadana, D and Rim, K and O'Neil, P and Mo, R and Chan, K and Cabral, C and others, Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D, Digest. International Electron Devices Meeting,, :946--948, 2002.

84.         Kedzierski, Jakub and Nowak, Edward and Kanarsky, Thomas and Zhang, YING and Boyd, Diane and Carruthers, Roy and Cabral, Cyril and Amos, Rick and Lavoie, Christian and Roy, Ronnen and others, Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation, Digest. International Electron Devices Meeting,, :247--250, 2002.

85.         Ren, Z and Ieong, M and Cai, J and Holt, J and Boyd, D and Mo, R and Yin, H and Dokumaci, O and Kawanaka, S and Sato, T, 30.7 Selective Epitaxial Channel Ground Plane Thin SOI CMOS Devices, INTERNATIONAL ELECTRON DEVICES MEETING, :751.

86.         Tang, Ting-Wei and Ieong, Mei-Kei, Discretization of flux densities in device simulations using optimum artificial diffusivity, IEEE transactions on computer-aided design of integrated circuits and systems, 14, (11), :1309--1315, 1995, IEEE.

87.         Ren, Zhibin and Ieong, M and Cai, J and Holt, J and Boyd, D and Mo, R and Yin, H and Dokumaci, O and Kawanaka, S and Sato, T and others, Selective epitaxial channel ground plane thin SOI CMOS devices, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., :733--736, 2005.

88.         Frank, MM and Paruchuri, VK and Narayanan, V and Bojarczuk, N and Linder, B and Zafar, S and Cartier, EA and Gusev, EP and Jamison, PC and Lee, KL and others, Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005.(VLSI-TSA-Tech)., :97--98, 2005.

89.         Ouyang, Qiqing and Yang, Min and Holt, Judson and Panda, Siddhartha and Chen, Huajie and Utomo, Henry and Fischetti, Massimo and Rovedo, Nivo and Li, Jinghong and Klymko, Nancy and others, Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., :28--29, 2005.

90.         Topol, Anna W and La Tulipe, DC and Shi, Leathen and Frank, David J and Bernstein, Kerry and Steen, Steven E and Kumar, Arvind and Singco, Gilbert U and Young, Albert M and Guarini, Kathryn W and others, Three-dimensional integrated circuits, IBM Journal of Research and Development, 50, (4.5), :491--506, 2006, IBM.

91.         Shang, Huiling and Lee, Kam-Leung and Kozlowski, P and D'emic, C and Babich, I and Sikorski, E and Ieong, Meikei and Wong, H-SP and Guarini, Kathryn and Haensch, W, Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate, IEEE Electron Device Letters, 25, (3), :135--137, 2004, IEEE.

92.         Shang, Huiling and Frank, Martin M and Gusev, Evgeni P and Chu, Jack O and Bedell, Stephen W and Guarini, Kathryn W and Ieong, Meikei, Germanium channel MOSFETs: Opportunities and challenges, IBM Journal of Research and Development, 50, (4.5), :377--386, 2006, IBM.

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94.         Kim, YH and Cabral, C and Gusev, EP and Carruthers, R and Gignac, L and Gribelyuk, M and Cartier, E and Zafar, S and Copel, M and Narayanan, V and others, Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., :4--pp, 2005.

95.         Shang, Huiling and Gousev, M and Gribelyuk, M and Chu, JO and Mooney, PM and Wang, X and Guarini, KW and Ieong, M, Fabrication, device design and mobility enhancement of germanium channel MOSFETs, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004., 1, :306--309, 2004.

96.         Pei, Gen and Kedzierski, Jakub and Oldiges, Phil and Ieong, Meikei and Kan, EC-C, FinFET design considerations based on 3-D simulation and analytical modeling, IEEE Transactions on Electron Devices, 49, (8), :1411--1419, 2002, IEEE.

97.         Ieong, Meikei and Guarini, Kathryn W and Chan, Victor and Bernstein, Kerry and Joshi, Rajiv and Kedzierski, Jakub and Haensch, Wilfred, Three dimensional CMOS devices and integrated circuits, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., :207--213, 2003.

98.         Singh, DV and Sleight, JW and Hergenrother, JM and Ren, Z and Jenkins, Keith A and Dokumaci, O and Black, L and Chang, JB and Nakayama, H and Chidambarrao, D and others, Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., :505--508, 2005.

99.         Chan, Victor and Rim, Ken and Ieong, Meikei and Yang, Sam and Malik, Rajeev and Teh, Young Way and Yang, Min and others, Strain for CMOS performance improvement, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005., :667--674, 2005.

100.     Doris, B and Zhang, Y and Fried, D and Beintner, J and Dokumaci, O and Natzle, W and Zhu, H and Boyd, D and Holt, J and Petrus, J and others, A simplified hybrid orientation technology (SHOT) for high performance CMOS, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., :86--87, 2004.

101.     Yang, Min and Chan, Victor WC and Chan, Kevin K and Shi, Leathen and Fried, David M and Stathis, James H and Chou, Anthony I and Gusev, Evgeni and Ott, John A and Burns, Lindsay E and others, Hybrid-orientation technology (HOT): Opportunities and challenges, IEEE Transactions on Electron Devices, 53, (5), :965--978, 2006, IEEE.

102.     Woolard, DL and Tian, H and Littlejohn, MA and Kim, KW and Trew, RJ and Ieong, MK and Tang, TW, Construction of higher-moment terms in the hydrodynamic electron-transport model, Journal of applied physics, 74, (10), :6197--6207, 1993, American Institute of Physics.

103.     Doris, Bruce and Ieong, Meikei and Kanarsky, Thomas and Zhang, Ying and Roy, Ronnen A and Dokumaci, Omer and Ren, Zhibin and Jamin, Fen-Fen and Shi, Leathen and Natzle, Wesley and others, Extreme scaling with ultra-thin Si channel MOSFETs, Digest. International Electron Devices Meeting,, :267--270, 2002.

104.     Lee, KL and Cardone, F and Saunders, P and Kozlowski, P and Ronsheim, PA and Zhu, H and Li, J and Chu, JO and Chan, KK and Ieong, M, 20 nm N+ abrupt junction formation in Strained Si/Si 1-xGe x MOS device, IEEE International Electron Devices Meeting, 2003.

105.     Yang, M and Ieong, M and Shi, L and Chan, K and Chan, V and Chou, A and Gusev, E and Jenkins, K and Boyd, D and Ninomiya, Y and others, High performance CMOS fabricated on hybrid substrate with different crystal orientations, IEEE International Electron Devices Meeting 2003, :18--7, 2003.

106.     Zafar, S and Yang, M and Gusev, E and Callegari, A and Stathis, J and Ning, T and Jammy, R and Ieong, M, A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/HfO/sub 2/), IEEE VLSI-TSA International Symposium on VLSI Technology, 2005.(VLSI-TSA-Tech)., :128--129, 2005.

107.     Shang, Huiling and Ieong, Meikei and Chu, Jack Oon and Guarini, Kathryn W, Integration of strained Ge into advanced CMOS technology, 2007.

108.     Lin, Tay-Jyi and Chien, Cheng-An and Chang, Pei-Yao and Chen, Ching-Wen and Wang, Po-Hao and Shyu, Ting-Yu and Chou, Chien-Yung and Luo, Shien-Chun and Guo, Jiun-In and Chen, Tien-Fu and others, A 0.48 V 0.57 nJ/pixel video-recording SoC in 65nm CMOS, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, :158--159, 2013.

109.     Shang, H and Gusev, EP and Frank, MM and Chu, JO and Bedell, S and Gribelyuk, M and Ott, JA and Wang, X and Guarini, KW and Ieong, M, Opportunities and Challenges of Germanium Channel MOSFETs, Advanced Gate Stacks for High-Mobility Semiconductors, :315--332, 2007, Springer Berlin Heidelberg.

110.     Singh, DV and Hergenrother, JM and Sleight, JW and Ren, Z and Nayfeh, H and Dokumaci, O and Black, L and Chidambarrao, D and Venigalla, R and Pan, J and others, Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths, 2005 IEEE International SOI Conference Proceedings, :178--179, 2005.

111.     Ieong, Meikei and Wong, H-SP and Nowak, Edward and Kedzierski, Jakub and Jones, Erin C, High performance double-gate device technology challenges and opportunities, Proceedings International Symposium on Quality Electronic Design, :492--495, 2002.

112.     Ieong, Meikei and Doris, Bruce and Kedzierski, Jakub and Ren, Zhibin and Rim, Ken and Yang, Min and Shang, Huiling and Chang, Leland, Device and substrate design for sub-10 nm MOSFETs, Proceedings-Electrochemical Society, :371--382, 2004.

113.     Guarini, KW and Topol, AW and Ieong, M and Yu, R and Shi, L and Newport, MR and Frank, DJ and Singh, DV and Cohen, GM and Nitta, SV and others, Electrical integrity of state-of-the-art 0.13/spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication, Digest. International Electron Devices Meeting,, :943--945, 2002.

114.     Rainey, BA and Fried, DM and Ieong, M and Kedzierski, J and Nowak, EJ, Demonstration of FinFET CMOS circuits, 60th DRC. Conference Digest Device Research Conference, :47--48, 2002.

115.     Ieong, MeiKei and Solomon, Paul M and Laux, SE and Wong, H-SP and Chidambarrao, Dureseti, Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model, International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), :733--736, 1998.

116.     Topol, A and Sheraw, C and Wong, K and Shao, X and Knarr, R and Rossnagel, SM and Yang, C-C and Baker-O'Neal, BC and Simon, A and Haran, B and others, Lower resistance scaled metal contacts to silicide for advanced CMOS, IEEE Symposium on VLSI Technology, 2006.

117.     Yang, Min and Chan, KK and Kumar, A and Lo, S-H and Sleight, J and Chang, L and Rao, R and Bedell, SW and Ray, A and Ott, JA and others, Silicon-on-insulator MOSFETs with hybrid crystal orientations, IEEE Symposium on VLSI Technology, 2006.

118.     Chen, TC and Shahidi, G and Guha, S and Ieong, M and Chudzik, MP and Jammy, R and Ronsheim, P and Batson, PE and Wang, Y and Lacey, DL and others, Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :178--179, 2006.

119.     Ieong, Meikei, Semiconductor industry driven by applications: artificial intelligence and internet-of-things, 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), :1--2, 2018.

120.     Ieong, M and Sung, CY and Deshpande, S and Chen, X and Deligianni, L and Cohen, S and Brodsky, C and Allen, S and Ouyang, C and Li, Y and others, Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :S--Cohen, 2006.

121.     Abe, David and Fang, Weileun and Horng, Ray-Hua and Iannaccone, Giuseppe and Ieong, Meikei and BV, TSMC Europe and Amsterdam, Netherlands Safa Kasap and Kimoto, Tsunenobu and Lord, Susan and Selmi, Luca, 2015 IEEE/EDS Fellows,.

122.     Shahidi, G and Ieong, M and Dalton, T and Gibson, G and Tornello, J and Deligianni, L and Canaperi, D and Medd, S and Maurer, S and Graham, W and others, Silicon-on-Insulator MOSFETs with Hybrid Crystal Orientations, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., :R--Meyer, 2006.

123.     Jones, Erin C and Ieong, Meikei and Kanarsky, Thomas and Dokumaci, Omer and Roy, Ronnen A and Shi, Leathen and Furukawa, Toshiharu and Miller, Robert J and Wong, H-S Philip, Planar Double Gate MOSFETs with Thin Backgate Oxides,.

124.     Lee, KL and Cardone, F and Saunders, P and Kozlowski, P and Ronsheim, P and Zhu, H and Li, J and Chu, J and Chan, K and Ieong, M, Sub-30 NM abrupt junction formation in strained silicon/silicon-germanium CMOs device, Advanced Short-time Thermal Processing for Si-based CMOS Devices 2: Proceedings of the International Symposium, 2004, (1), :71, 2004.

125.     Jammy, R and Narayanan, V and Frank, MM and Paruchuri, VK and Callegari, AC and Gusev, E and Cabral, C and Linder, BP and Zafar, S and Cartier, E and others, Optimization of high $\kappa$ gate stacks with poly-Si, FUSI and metal electrodes, International Conference on Semiconductor Technology, 2005.

126.     Zhuang, Haoren and Wang, Helen and Yap, Chin Chin and Gutmann, Alois and Lian, Jingyu and Sarma, Chandrasekhar and Tsou, Len and Gabor, Allen H and Schroeder, Uwe Paul and Halle, Scott and others, Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond, International Conference on Semiconductor Technology, 2007.

127.     La Tulipe, DC and Shi, LT and Topol, A and Frank, DJ and Steen, SE and Pfeiffer, D and Posillico, D and Neumayer, D and Goma, S and Vichiconti, J and others, Critical aspects of layer transfer and alignment tolerances for 3D integration processes, Spring Conference on Global Business Council, 2006.

128.     Yang, M and Schaub, J and Rogers, DL and Griesemer, JA and Boyd, D and Zhang, B and Rodier, F and Flaitz, P and McMurray, JS and Chan, KK and others, Integration of 1GB/sec Silicon Lateral Trench Photodetector with High-Performance CMOS, IEEE Symposium on VLSI Technology, 2003.

129.     Topol, A and La Tulipe, DC and Shi, LT and Alam, SM and Young, A and Frank, DJ and Steen, SE and Vichiconti, J and Posillico, D and Canapeti, D and others, Assembly technology for three dimensional integrated circuits, International VLSI Multilevel Interconnection Conference, 2005.

Research Grants

Newly Approved  基於UWB超寬頻的AI物聯網輔助自主系統(FDCT)

Patents

1.             U.S. Patent US7018891B2, Ultra-thin Si channel CMOS with improved series resistance.

2.             U.S. Patent US6677646B2, Method and structure of a disposable reversed spacer.

3.             U.S. Patent US7041538B2, Method of manufacturing a disposable reversed spacer.

4.             U.S. Patent US7482243B2, Ultra-thin Si channel MOSFET using a self-aligned oxygen.

5.             U.S. Patent US7075150B2, Ultra-thin Si channel MOSFET using a self-aligned oxygen.

6.             U.S. Patent US20070040235A1, Dual trench isolation for CMOS with hybrid orientations.

7.             U.S. Patent US8097516B2, Dual trench isolation for CMOS with hybrid orientations.

8.             U.S. Patent US20080036028A1, Dual trench isolation for CMOS with hybrid orientations.

9.             U.S. Patent US9355887B2, Dual trench isolation for CMOS with hybrid orientations.

10.         U.S. Patent US6914303B2, Ultra thin channel MOSFET.

11.         U.S. Patent US7211490B2, Ultra thin channel MOSFET.

12.         U.S. Patent US20070010070A1, Fabrication of strained semiconductor-on-insulator.

13.         U.S. Patent US20030067017A1, Variable threshold voltage double gated transistors and method of.

14.         U.S. Patent US6492212B1, Variable threshold voltage double gated transistors and method of.

15.         U.S. Patent US7354806B2, Semiconductor device structure with active regions having.

16.         U.S. Patent US20080142852A1, Semiconductor device structure with active regions having.

17.         U.S. Patent US7183182B2, Method and apparatus for fabricating CMOS field effect.

18.         U.S. Patent US20070128785A1, Method and apparatus for fabricating CMOS field effect.

19.         U.S. Patent US7002214B1, Ultra-thin body super-steep retrograde well (SSRW) FET.

20.         U.S. Patent US7091069B2, Ultra thin body fully-depleted SOI MOSFETs.

21.         U.S. Patent US7547641B2, Super hybrid SOI CMOS devices.

22.         U.S. Patent US7459752B2, Ultra thin body fully-depleted SOI MOSFETs.

23.         U.S. Patent US7388259B2, Strained finFET CMOS device structures.

24.         U.S. Patent US7619300B2, Super hybrid SOI CMOS devices.

25.         U.S. Patent US7687829B2, Stressed field effect transistors on hybrid orientation substrate.

26.         U.S. Patent US7525161B2, Strained MOS devices using source/drain epitaxy.

27.         U.S. Patent US7405436B2, Stressed field effect transistors on hybrid orientation substrate.

28.         U.S. Patent US7678638B2, Metal gated ultra short MOSFET devices.

29.         U.S. Patent US6905941B2, Structure and method to fabricate ultra-thin Si channel devices.

30.         U.S. Patent US7494861B2, Method for metal gated ultra short MOSFET devices.

31.         U.S. Patent US20050003589A1, Structure and method to fabricate ultra-thin Si channel devices.

32.         U.S. Patent US7348629B2, Metal gated ultra short MOSFET devices.

33.         U.S. Patent US6911383B2, Hybrid planar and finFET CMOS devices.

34.         U.S. Patent US20050263831A1, Hybrid planar and FinFET CMOS devices.

35.         U.S. Patent US7247569B2, Ultra-thin Si MOSFET device structure and method of.

36.         U.S. Patent US20070228473A1, ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND.

37.         U.S. Patent US7329923B2, High-performance CMOS devices on hybrid crystal oriented.

38.         U.S. Patent US7385257B2, Hybrid orientation SOI substrates, and method for forming the same.

39.         U.S. Patent US7713807B2, High-performance CMOS SOI devices on hybrid crystal-oriented.

40.         U.S. Patent US7834425B2, Hybrid orientation SOI substrates, and method for forming the same.

41.         U.S. Patent US6833569B2, Self-aligned planar double-gate process by amorphization.

42.         U.S. Patent US20050145837A1, Enhancement of electron and hole mobilities in <110> Si.

43.         U.S. Patent US7259049B2, Self-aligned isolation double-gate FET.

44.         U.S. Patent US20080044987A1, ENHANCEMENT OF ELECTRON AND HOLE.

45.         U.S. Patent US7314790B2, Enhancement of electron and hole mobilities in Si under biaxial.

46.         U.S. Patent US7943486B2, Enhancement of electron and hole mobilities in Si under biaxial.

47.         U.S. Patent US20080042202A1, QUASI SELF-ALIGNED SOURCE/DRAIN FinFET.

48.         U.S. Patent US7402466B2, Strained silicon CMOS on hybrid crystal orientations.

49.         U.S. Patent US7087965B2, Strained silicon CMOS on hybrid crystal orientations.

50.         U.S. Patent US6946696B2, Self-aligned isolation double-gate FET.

51.         U.S. Patent US7691688B2, Strained silicon CMOS on hybrid crystal orientations.

52.         U.S. Patent US7462525B2, Enhancement of electron and hole mobilities in Si under biaxial.

53.         U.S. Patent US7094634B2, Structure and method for manufacturing planar SOI.

54.         U.S. Patent US7384851B2, Buried stress isolation for high-performance CMOS technology.

55.         U.S. Patent US7023055B2, CMOS on hybrid substrate with different crystal orientations using.

56.         U.S. Patent US6271094B1, Method of making MOSFET with high dielectric constant gate.

57.         U.S. Patent US7364958B2, CMOS on hybrid substrate with different crystal orientations using.

58.         U.S. Patent US20020028555A1, Mosfet with high dielectric constant gate insulator and.

59.         U.S. Patent US7691482B2, Structure for planar SOI substrate with multiple orientations.

60.         U.S. Patent US9236445B2, Transistor having replacement gate and epitaxially grown.

61.         U.S. Patent US20070170507A1, STRUCTURE AND METHOD FOR MANUFACTURING.

62.         U.S. Patent US7023057B2, CMOS on hybrid substrate with different crystal orientations using.

63.         U.S. Patent US7220626B2, Structure and method for manufacturing planar strained.

64.         U.S. Patent US7605447B2, Highly manufacturable SRAM cells in substrates with hybrid.

65.         U.S. Patent US7704839B2, Buried stress isolation for high-performance CMOS technology.

66.         U.S. Patent US7833854B2, Structure and method of fabricating a hybrid substrate for.

67.         U.S. Patent US20080042140A1, Three dimensional integrated circuit and method of design.

68.         U.S. Patent US6830962B1, Self-aligned SOI with different crystal orientation using wafer.

69.         U.S. Patent US8158481B2, CMOS structure and method for fabrication thereof using multiple.

70.         U.S. Patent US7671421B2, CMOS structure and method for fabrication thereof using multiple.

71.         U.S. Patent US7723207B2, Three dimensional integrated circuit and method of design.

72.         U.S. Patent US7268377B2, Structure and method of fabricating a hybrid substrate for.

73.         U.S. Patent US7138683B2, Self-aligned SOI with different crystal orientation using WAFER.

74.         U.S. Patent US7425483B2, Structure and method of fabricating a hybrid substrate for.

75.         U.S. Patent US20070287256A1, Contact scheme for FINFET structures with multiple FINs.

76.         U.S. Patent US7141457B2, Method to form Si-containing SOI and underlying substrate with.

77.         U.S. Patent US8080838B2, Contact scheme for FINFET structures with multiple FINs.

78.         U.S. Patent US8785281B2, CMOS structure and method for fabrication thereof using multiple.

79.         U.S. Patent US7759772B2, Method to form Si-containing SOI and underlying substrate with.

80.         U.S. Patent US7312487B2, Three dimensional integrated circuit.

81.         U.S. Patent US7244958B2, Integration of strained Ge into advanced CMOS technology.

82.         U.S. Patent US7675055B2, Strained complementary metal oxide semiconductor (CMOS) on.

83.         U.S. Patent US20020197810A1, Mosfet having a variable gate oxide thickness and a variable.

84.         U.S. Patent US7387925B2, Integration of strained Ge into advanced CMOS technology.

85.         U.S. Patent US7291886B2, Hybrid substrate technology for high-mobility planar and multiple-.

86.         U.S. Patent US7528056B2, Low-cost strained SOI substrate for high-performance CMOS.

87.         U.S. Patent US6815278B1, Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator.

88.         U.S. Patent US7790538B2, Integration of strained Ge into advanced CMOS technology.

89.         U.S. Patent US7485506B2, Hybrid substrate technology for high-mobility planar and multiple-.

90.         U.S. Patent US7098508B2, Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator.

91.         U.S. Patent US7348611B2, Strained complementary metal oxide semiconductor (CMOS) on.

92.         U.S. Patent US7288445B2, Double gated transistor and method of fabrication.

93.         U.S. Patent US6762469B2, High performance CMOS device structure with mid-gap metal gate.

94.         U.S. Patent US6916698B2, High performance CMOS device structure with mid-gap metal gate.

95.         U.S. Patent US7960790B2, Self-aligned planar double-gate transistor structure.

96.         U.S. Patent US7205185B2, Self-aligned planar double-gate process by self-aligned oxidation.

97.         U.S. Patent US7453123B2, Self-aligned planar double-gate transistor structure.

98.         U.S. Patent US7413941B2, Method of fabricating sectional field effect devices.

99.         U.S. Patent US7659153B2, Sectional field effect devices and method of fabrication.

100.     U.S. Patent US20050067620A1, Three dimensional CMOS integrated circuits having device.

101.     U.S. Patent US7482216B2, Substrate engineering for optimum CMOS device.

102.     U.S. Patent US6960806B2, Double gated vertical transistor with different first and second.

103.     U.S. Patent US6821826B1, Three dimensional CMOS integrated circuits having device.

104.     U.S. Patent US7645650B2, Double gated transistor and method of fabrication.

105.     U.S. Patent US7388258B2, Sectional field effect devices.

106.     U.S. Patent US6466489B1, Use of source/drain asymmetry MOSFET devices in dynamic and.

107.     U.S. Patent US7309626B2, Quasi self-aligned source/drain FinFET process.

108.     U.S. Patent US60534916P0, Enhancement of electron and hole mobilities in Si under biaxial.

109.     China Patent CN100419999C, 制造CMOS场效应晶体管的方法和设备.

110.     China Patent CN1728402B, 超薄型本体超陡后退阱场效应晶体管器件及其制造方法.

111.     China Patent CN100378901C, 应变鳍型场效应晶体管互补金属氧化物半导体器件结构.

112.     China Patent CN1292473C, 混合平面和FinFET CMOS器件.

113.     China Patent CN101236968B, MOS器件及其制造方法.

114.     China Patent CN100428475C, 具有提高的载流子迁移率的半导体结构及其制造方法.

115.     China Patent CN100479191C, MOSFET器件及其制造方法.

116.     China Patent CN100536144C, 半导体器件、半导体器件的衬底结构及其形成方法.

117.     China Patent CN100544022C, 具有晶体取向含硅层的半导体材料及其形成方法.

118.     China Patent CN100378917C, 制造应变含硅混合衬底的方法以及含硅混合衬底.

119.     China Patent CN100361302C, 混合衬底、集成半导体结构以及它们的制备方法.

120.     China Patent CN100424853C, 三维集成电路及其设计方法.

121.     China Patent CN100411180C, 半导体结构及制造半导体结构的方法.

122.     China Patent CN1300853C, 制作集成半导体结构的方法.

123.     China Patent CN100508194C, 半导体结构以及制造半导体结构的方法.

124.     China Patent CN100505276C, 应变绝缘硅.

125.     China Patent CN101256949B, 应变SOI衬底的制造方法和在其上制造CMOS器件的方法.

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Professional Certification and Awards

-            “2023 VLSI Test of Time Award” at the Symposium of VLSI Technology and Circuits Symposium that recognises papers that have established their significance in history by standing the test of time.

-            Taiwan Innovation Award for TSMC’s 28nm High-k/Metal gate technology.

-            IBM Master Inventor Award

-            IBM Outstanding Technical Achievement Award

-            IBM Corporate Award

Professional Society Membership

IEEE Fellow